Multiple error correction codes (ECCs) are implemented in contemporary flash controllers to adapt to the fact that bit error rate (BER) increases and signal-to-noise ratio (SNR) decreases over program and erase (P/E) cycles. An accurate policy to decide when to switch from a weaker ECC to a stronger ECC over P/E cycles is needed. Unlike traditional Bose-Chaudhuri-Hocquenghem (BCH) codes, there is no hard limit for the maximum number of errors that can be corrected by hard-decision low density parity check (LDPC) codes. Deciding when to switch from a weaker LDPC code to a stronger LDPC code based on the number of errors being corrected is difficult. Switching to a stronger LDPC code based on real-time testing of the number of uncorrectable error correction codes (UECCs) can result in the switch occurring too late or too early. For hard LDPC only products (with less implementation cost), testing of UECC failure rate in real-time is not acceptable.
It would be desirable to have a method and/or apparatus for implementing error correction code (ECC) selection in NAND flash controllers with multiple ECCs.